Vlsi Project Center in chennai

IEEE 2016 - 2017 VLSI Projects
16.A High Throughput List Decoder Architecture For Polar Codes





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17.High-Performance NB-LDPC Decoder With Reduction of Message Exchange





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18.A High-Speed FPGA Implementationof an RSD-Based ECC Processor





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19.Low-Power ECG-Based Processor forPredicting Ventricular Arrhythmia





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20.In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers





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21.Configurable Parallel Hardware Architecture forEfficient Integral Histogram Image Computing





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22.Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding





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23.A Normal I/O Order Radix-2 FFT Architecture to ProcessTwin Data Streams for MIMO





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24.Unequal-Error-Protection Error Correction Codes for theEmbedded Memories in Digital Signal Processors





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25.A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications





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26.Hybrid LUT/Multiplexer FPGA Logic Architectures





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27.A Dynamically Reconfigurable Multi-ASIP Architecture forMultistandard and Multimode Turbo Decoding





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28.Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units





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29.A Fully Digital Front-End Architecture for ECGAcquisition System With 0.5 V Supply





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30.A Low-cost and Modular Receiver for MIMO SDR





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