IEEE 2016 - 2017 VLSI Projects

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IEEE 2016 - 2017 VLSI Projects
1.A Modified Partial Product Generator for Redundant Binary Multipliers





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2.An Efficient Hardware Implementation of Canny Edge Detection Algorithm





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3.Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation





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4.A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications





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5.The Serial Commutator (SC) FFT





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6.An Improved Signed Digit Representation Approach for Constant Vector Multiplication





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7.High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels





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8.A New XOR-Free Approach for Implementation of Convolutional Encoder





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9.Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology





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10.Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation





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11.Implementation of a PID control PWM Module on FPGA





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12.Built-in Self Testing of FPGAs





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13.An FPGA-Based Cloud System for Massive ECG Data Analysis





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14.Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip





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15.VLSI Implementation of Fully Parallel LTE Turbo Decoders





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